Test device and test system of semiconductor device and test method for testing semiconductor device

ABSTRACT

A test device of a semiconductor device for testing semiconductor device including a plurality of interface pads includes a plurality of coupling units each configured to be coupled to a corresponding one of the plurality of interface pads, a channel configured to be coupled to the plurality of coupling units, a voltage generating unit configured to generate a test voltage applied to the channel, and a current measuring unit configured to measure a current that flows on the channel in response to the test voltage.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority of Korean Patent application No.10-2012-0050388, filed on May 11, 2012, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to a test deviceand a test system of a semiconductor device and a test method fortesting a semiconductor device.

2. Description of the Related Art

During a production process of a semiconductor device, a probe test isperformed to determine whether a memory cell of a semiconductor deviceon a wafer performs a read operation or a write operation correctly. Theprobe test determines a malfunction of the semiconductor device bycoupling a probe of a probe card to each pad of the semiconductor deviceon a wafer and inputting and outputting a power voltage and a signal.

However, it may be requested for a correct probe test to electricallycouple the probe of the probe card to each pad of the semiconductor, orinputting and outputting the power voltage and the signal of thesemiconductor device. Thus, it may be important to analyze an electricalcoupling between the probe of the probe card and each pad of thesemiconductor device.

In case of a conventional probe test for determining whether a probe ofa probe card is coupled to a pad of a semiconductor device or not, atest current flows through the probe coupled to the pad of thesemiconductor, and a voltage that is applied to the pad of thesemiconductor device is measured in response to the test current. Here,a predetermined voltage level is measured if the probe is coupled to thepad of the semiconductor device, and a predetermined voltage is notmeasured if the probe is not coupled to the pad of the semiconductordevice. In other words, if the probe is not coupled to the pad of thesemiconductor device, a measured voltage level has a lowest value of avoltage measurement range.

Meanwhile a plurality of probes is used in one channel of a test devicebecause of a limited number of channels of a test device during a probetest. Thus, it is requested to analyze an electrical coupling betweenthe plurality of probes and a plurality of interface pads of thesemiconductor device before the probe test is performed.

In a case of conventional probe test method, after a test current flowsto a plurality of probes coupled to each pad of the semiconductordevice, an electrical coupling is analyzed between the plurality ofprobes and each pad of the semiconductor by using a voltage outputted inresponse to the test current. However, because a plurality of probes iscoupled to one channel of the test device in parallel, a voltage ismeasured although one of the plurality of probes is coupled to a pad ofa semiconductor device. The voltage may be maintained constantlyirrespective of a number of the probes that is coupled to the pad.Furthermore, the voltage is measured irrespective of a coupling strengthstate between the probes and the pad. Thus, it may be difficult toanalyze whether each of probes is coupled to the pad or not and analyzea coupling strength state between each of probes and the pad.

SUMMARY

Exemplary embodiments of the present invention are directed to a testdevice and a test system of a semiconductor device, and a method fortesting a semiconductor device, including analyzing a coupling statebetween a plurality of probes and a plurality of pads of a semiconductordevice, and analyzing a coupling strength state between each pad of thesemiconductor device and the plurality of probes by applying a testvoltage to the plurality of probes, and measuring a current that flowson the plurality of probes in response to the test voltage.

In accordance with an exemplary embodiment of the present invention, atest device of a semiconductor device for testing a semiconductor devicehaving a plurality of interface pads, includes a plurality of couplingunits, each configured to be coupled to a corresponding one of theplurality of interface pads, a channel configured to be coupled to theplurality of coupling units, a voltage generating unit configured togenerate a test voltage applied to the channel, and a current measuringunit configured to measure a current that flows on the channel inresponse to the test voltage

In accordance with another exemplary embodiment of the presentinvention, a test system of a semiconductor device includes asemiconductor device configured to includes a plurality of interfacepads for inputting or outputting a signal; and a test device including aplurality of coupling units, each configured to be coupled to acorresponding one of the plurality of interface pads, and a channelcoupled to the plurality of coupling units, wherein the test deviceapplies a test voltage to the channel and measures a current that flowson the channel in response to the test voltage.

In accordance with still another exemplary embodiment of the presentinvention, a test method for testing a semiconductor device having aplurality of interface pads includes coupling a plurality of couplingunits to a plurality of interface pads; applying a test voltage to achannel coupled to the plurality of coupling units and measuring acurrent that flows on the channel in response to the test voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a test device in accordance with anembodiment of the present application.

FIG. 2 is a diagram illustrating a test system in accordance with anembodiment of the present application.

FIG. 3 is a diagram illustrating a test method of a semiconductor devicein accordance with an embodiment of the present application.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the present invention tothose skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

FIG. 1 is a diagram illustrating a test device in accordance with anembodiment of the present application.

As shown in FIG. 1, a test device 100 of a semiconductor device 200including a plurality of interface pads P1 to P3, includes a pluralityof coupling units N1 to N3, a channel CH configured to be coupled to theplurality of coupling units N1 to N3, a voltage generating unit 110, acurrent measuring unit 120 and a result analyzing unit 130, The voltagegenerating unit 110 generates a test voltage VT, and the test voltage VTis applied to the channel H. The current measuring unit 120 measures acurrent IT that flows on the channel CH in response to the test voltageVT, The result analyzing unit 130 analyzes whether each of the pluralityof coupling units N1 to N3 is coupled to each of the plurality ofinterface pads P1 to P3 or not by using the test voltage VT and thecurrent IT. The result analyzing unit 130 analyzes a coupling strengthbetween the plurality of coupling units N1 to N3 and the plurality ofinterface pads P1 to P3.

In another embodiment of the present application, the coupling units N1to N3 may be probes that are coupled to a channel of a probe card.

As referring to FIG, 1, the test device 100 for testing thesemiconductor device applies a plurality of signals to the semiconductordevice 200, analyzes a signal output from the semiconductor device 200,and generates a test result of the semiconductor device 200.

Since this application relates to analyze a coupling state between theplurality of coupling units N1 to N3 coupled to the channel CH and theplurality of interface pads P1 to P3, it will be omitted that theplurality of signals is applied to the semiconductor device 200, and anoutput signal of the semiconductor device 200 is analyzed.

The test device 100 couples the plurality of coupling units N1 to N3 tothe plurality of interface pads P1 to P3, and tests a fully couplingstate between the plurality of coupling units N1 to N3 and the pluralityof interface pads P1 to P3. The fully coupling state indicates that theplurality of coupling units N1 to N3 is electrically coupled to theplurality of interface pads P1 to P3 with a predetermined couplingstrength. In the fully coupling state, there is no problem for testingthe semiconductor device 200 by analyzing a signal output from thesemiconductor device after the test device 100 applies a predeterminedsignal to the semiconductor device 200.

Hereinafter, it is referred to as ‘a coupling test’ for analyzing thefully coupling state between the plurality of coupling units N1 to N3and the plurality of interface pads P1 to P3.

During the coupling test, the voltage generating unit 110 generates thetest voltage VT that is applied to the channel CH coupled to theplurality of coupling units NI to N3. The test voltage VT is transferredto the plurality of coupling units N1 to N3 through the channel CH andis applied to the plurality of interface pads PI to P3 through theplurality of coupling units N1 to N3.

When each of the plurality of coupling units N1 to N3 is coupled to eachof the interface pads P1 to P3, a voltage level of the test voltage VTis required so that the current measuring unit 120 of the test device100 can correctly measure a current that flows on the plurality ofinterface pads P1 to P3 in response to the test voltage VT.

For example if the test voltage VT has a very low voltage lever becausea current does not flow on the plurality of interface pads P1 to P3, itmay be difficult to correctly measure the coupling state and a currentvariation between the plurality of coupling units N1 to N3 and theplurality of interface pads P1 to P3. If the test voltage VT has a veryhigh voltage level, because an over-current flows on the plurality ofinterface pads P1 to P3, the test device 100 and the semiconductordevice 200 may be damaged.

The current measuring unit 120 measures the current that flows on thechannel CH in response to the test voltage VT. The plurality of couplingunits N1 to N3 is coupled to one channel that is one node in view of anelectronic circuit. In other words, the plurality of coupling units N1to N3 is coupled to one node in parallel. Thus, the amount of a currentthat flows on the channel, is a sum of the amount of the current thatflows between each of the plurality of coupling units N1 to N3 and eachof the plurality of interface pads P1 to P3 coupled to the each of theplurality of coupling units N1 to N3 in response to the test voltage VT.

The amount of the current that flows between one coupling unit and oneinterface pad coupled to the coupling unit is determined by a couplingstrength between the coupling unit and the interface pad. As thecoupling strength between the coupling unit and the interface pad isincreased, a resistance value of a path on which a current flows isdecreased and the amount of the current between the coupling unit andthe interface pad is increased. As the coupling strength between thecoupling unit and the interface pad is decreased, a resistance value ofthe path on which the current flows is increased and the amount of thecurrent between the coupling unit and the interface pad is decreased.When the coupling unit is not coupled to the interface pad, the currentdoes not flows between the coupling unit and the interface pad.

Moreover, as the current that flows between each of the plurality ofcoupling units N1 to N3 and each of the plurality of to interface padsP1 to P3 is increased and a number of the coupling units N1 to N3 isincreased, the amount of the current that flows on the channel CH inresponse to the test voltage VT is increased. In other words, as each ofthe plurality of coupling units N1 to N3 is strongly coupled to each ofthe plurality of interface pads P1 to P3 and the number of interfacepads P1 to P3 coupled to the each of the coupling units N1 to N3 isincreased, the amount of the current that flows on the channel CH inresponse to the test voltage VT is increased.

As shown in FIG. 1, a first coupling unit N1 is coupled to a firstinterface pad a second coupling unit N2 is coupled to a second interfacepad P2, a third coupling unit N3 is coupled to a third interface pad P3.

The amount of the current that flows on the channel CH is determinedaccording to a coupling strength between the first coupling unit N1 andthe first interface pad P1, a coupling strength between the secondcoupling unit N2 and the second interface pad P2, and a couplingstrength between the third coupling unit N3 and the third interface padP3.

In other words, as the coupling strength between the first coupling unitN1 and the first interface pad P1, between the second coupling unit N2and the second interface pad P2, and between the third coupling unit N3and the third interface pad P3 is increased, the amount of the currentthat flows on the channel CH is increased.

Although each of the plurality of coupling units N1 to N3 is fullycoupled to each of the plurality of interface pads P1 to P3, if acircuit including the plurality of interface pads N1 to N3 and theplurality of coupling units P1 to P3 is an open circuit, the currentdoes not flow between the plurality of interface pads Ni. to N3 and theplurality of coupling units P1 to P3, and each of the plurality ofinterface pads P1 to P3 is coupled to each of a plurality of currentpaths CP1 to CP3.

Each of the plurality of current paths CP1 to CP3 may include aresistive element (not shown) or a diode (not shown), each having aresistance value, so that the test device 100 and the semiconductordevice 200 are prevented from possible damage caused by an over-currentor malfunction of the current measuring unit 120 due to little amount ofthe current when the test voltage VT is applied.

An end of each current path CP1 to CP3 is coupled to each interface padP1 to P3, and the other end of each current path CP1 to CP3 is coupledto a power voltage supply terminal 201 or a ground voltage supplyterminal 202, shown in FIG. 2,

The result analyzing unit 130 analyzes a fully coupling between theplurality of coupling units N1 to N3 and the plurality of interface padsP1 to P3 by using the test voltage VT and the current that flows on thechannel CH in response to the test voltage VT. The result analyzing unit130 stores data relating to the amount of the current that flows on thechannel CH according to a coupling strength between each coupling unitN1 to N3 and each interface pad P1 to P3, and the amount of the currentthat flows on the channel CH according to a number of the coupling unitsN1 to N3 coupled to the interface pads P1 to P3. The result analyzingunit 130 compares the stored data with the test voltage VT applied tothe channel CH and a value measured by the current measuring unit 120,Also, the result analyzing unit 130 determines the number of thecoupling units N1 to N3 coupled to the interface pads P1 to P3 and thecoupling strength between each coupling unit N1 to N3 and each interfacepad P1 to P3 based on the compared result.

In case that the plurality of coupling units N1 to N3 that is coupled tothe plurality of interface pads P1 to P3 of the semiconductor device200, is coupled to the one channel CH during a coupling test, the testdevice 100 in accordance with an embodiment of the present applicationacquires the number of coupling units N1 to N3 coupled to the interfacepads P1 to P3 and the coupling strength between each coupling unit N1 toN3 and each interface unit P1 to P3. Thus, the test device 100 inaccordance with an embodiment of the present application improves theaccuracy of the coupling test highly.

In another embodiment of the present application, a number of channels,a number of coupling units coupled to one channel, and a number ofinterface pads may be changed according to a design of the test device.

FIG. 2 is a configuration diagram illustrating a test system inaccordance with an embodiment of the present application. A test systemof the semiconductor device 200 shown in FIG. 2 includes the test device100 shown in FIG. 1.

As shown in FIG. 2, the test system of the semiconductor device 200includes a semiconductor device 200 and a test device 100. Thesemiconductor device 200 includes a plurality of interface pads P1 to P3for inputting or outputting a signal. The test device 100 includes aplurality of coupling units N1 to N3 coupled to the plurality ofinterface pads P1 to P3, and a channel CH coupled to the plurality ofcoupling units N1 to N3. The test device 100 applies a test voltage VTto the channel CH and measures a current IT that flows on the channel CHin response to the test voltage VT.

Since a detailed configuration and operation of the test device 100 issimilar to that of the test device 100 shown in FIG. 1, the descriptionof the test device 100 is omitted.

The semiconductor device 200, as shown in FIG. 2, further includes aninternal circuit 210 and an electrostatic discharge circuit 220. Theinternal circuit 210 performs an intrinsic operation by using a signalthat is input or output through the plurality of interface pads P1 toP3. For example, in a semiconductor device, an internal circuit receivesa command, an address and data, and performs a read operation or a writeoperation. In an arithmetic device, an internal circuit receives aplurality of signals and performs an arithmetic operation. to Theelectrostatic discharge circuit 220 protects the internal circuit 210from an electrostatic that is input from the plurality of interface padsP1 to P3 and from a power noise that is input through the plurality ofinterface pads P1 to P3.

The electrostatic discharge circuit 220 includes a power voltage supplyterminal 201, a plurality of first diodes D11 to D13 a ground voltagesupply terminal 202 and a plurality of second diodes D21 to D23.

In case that a voltage of the plurality of interface pads P1 to P3 ishighly increased by receiving the electrostatic or the power noisethrough the plurality of interface pads P1 to P3, the power voltagesupply terminal 201 supplies a power voltage VDD to the internal circuit210 for discharging an electrostatic or a power noise. The plurality offirst diodes D11 to D13 is coupled to the plurality of interface pads P1to P3.

In case that a voltage of the plurality of interface pads P1 to P3 ishighly decreased, the ground voltage supply terminal 202 supplies aground voltage VSS to the internal circuit 210 for discharging adecreased voltage. The plurality of second diodes D21 to D23 is coupledto the plurality of interface pads P1 to P3.

The plurality of first diodes D11 to D13 is respectively turned on inresponse to the test voltage VT that is applied through the plurality ofcoupling units N1 to N3, when the interface pads P1 to P3 are coupled tothe plurality of coupling units N1 to N3. The current between theplurality of interface pads P1 to P3 and the power voltage supplyterminal 201 flows through the plurality of first diodes D11 to D13. Asdescribed above, the plurality of first diodes D11 to D13 performs anoperation of the current paths CP1 to CP3 shown in FIG. 1.

When the plurality of coupling units N1 to N3 is coupled to theplurality of interface pads P1 to P3, the test voltage VT may be avoltage higher than a voltage of sum of the power voltage VDD and athreshold voltage VTH (not shown) of one of the plurality of firstdiodes D11 to D13, so that the current flows through the plurality offirst diodes D11 to D13. A numerical expression of the correlation amongthe test voltage VT, a power voltage VDD and the threshold voltage VTHof one of the plurality of first diodes D11 to D13 is defined as‘VT≧VDD+VTH’.

If the test voltage VT is applied to the channel CH, the test voltage VTis transferred to the plurality of interface pads P1 to P3 via theplurality of coupling units N1 to N3. A voltage applied in a forwarddirection of the plurality of first diodes D11 to D13 is a differencevoltage between the test voltage VT and the power voltage VDD. If thecorrelation among the test voltage VT, the power voltage VDD and thethreshold voltage VTH of one of the plurality of diodes D11 to D13 issatisfied by the numerical expression of ‘VT≧VDD+VTH’, a current path isestablished between the power voltage supply terminal 201 and theplurality of interface pads P1 to P3 since the difference voltagebetween the test voltage VT and the power voltage VDD is higher than thethreshold voltage VTH of one of the plurality of diodes D11 to D13.

During the coupling test, an operation of the test device 100 is similarto that of the test device 100 shown in FIG. 1. Thus, the test system ofthe semiconductor device shown in FIG. 2 has a similar effect to thetest device 100 of the semiconductor device shown in FIG. 1.

FIG. 3 is a configuration diagram illustrating a test method of asemiconductor device in accordance with an embodiment of the presentapplication.

As shown in FIGS, 1 to 3, a test method of the semiconductor devicehaving the plurality of interface pads P1 to P3 includes coupling theplurality of coupling units N1 to N3 to the plurality of interface padsP1 to P3 (Hereinafter, ‘coupling step S310’), applying the test voltageVT to the channel CH coupled to the plurality of coupling units N1 to N3(Hereinafter, ‘voltage applying step S320’), measuring the current ITthat flows on the channel CH in response to the test voltage VT(hereinafter, ‘current measuring step S330’), and analyzing a couplingstate and a coupling strength between the plurality of coupling units N1to N3 and the plurality of interface pads P1 to P3 by using the testvoltage VT and the current IT (hereinafter, ‘analyzing step S340’).

Referring to FIGS. 1 to 3, in the coupling step S310, the to pluralityof coupling units N1 to N3 coupled to the channel CH of the test device100 is coupled to the plurality of interface pads P1 to P3 of thesemiconductor device. The coupling state between the plurality ofcoupling units N1 to N3 and the plurality of interface pads P1 to P3represents that the plurality of coupling units N1 to N3 is locatedwithin a predetermined range from the plurality of interface pads P1 toP3. The coupling state between the plurality of coupling units N1 to N3and the plurality of interface pads P1 to P3 is electrically checked asfollows.

When the coupling step S310 is completed, in the voltage applying stepS320, the test device 100 generates the test voltage VT and applies thetest voltage VT to the channel CH. The test voltage VT is then appliedto the plurality of interface pads P1 to P3 of the semiconductor device200 through the plurality of coupling units N1 to N3 that is coupled tothe channel CH.

Subsequently, the current flows between each of the plurality ofcoupling units N1 to N3 and each of the plurality of interface pads P1to P3 in response to the test voltage VT applied in the voltage applyingstep S320.

Since the plurality of coupling units N1 to N3 is coupled to the channelCH of one node in parallel, the current having the amount same as thesum of the current that flows between each of the plurality of couplingunits N1 to N3 and each of the plurality of interface pads P1 to P3,flows on the channel CH.

In the current measuring step S330, the test device 100 measures theamount of the current that flows on the channel CH in response to thetest voltage VT. The amount of the current that flows on the channel CHis increased as the number of the coupling units N1 to N3 coupled to theinterface pads P1 to P3 is increased and the coupling strength betweenthe coupling units N1 to N3 and the interface pads P1 to P3 isincreased.

In the analyzing step S340, the'test device 100 analyzes the couplingstate and the coupling strength between the plurality of coupling unitsN1 to N3 and the plurality of interface pads P1 to P3 based on the testvoltage VT applied in the voltage applying step S320 and the currentmeasured in the current measuring step S330,

The test method of the semiconductor device in accordance with anembodiment of the present application has a same effect as the testdevice of the semiconductor device shown in FIG. 1.

While the present invention has been described with respect to thespecific embodiments it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1-5. (canceled)
 6. A test system of a semiconductor device, comprising:a semiconductor device including a plurality of interface pads forinputting or outputting a signal; and a test device including aplurality of coupling units, each configured to be coupled to acorresponding one of the plurality of interface pads, and a channelcoupled to the plurality of coupling units, wherein the test deviceapplies a test voltage to the channel and measures a current that flowson the channel in response to the test voltage.
 7. The test system ofthe semiconductor device of claim 6, further comprising: a voltagegenerating unit configured to generate the test voltage applied to thechannel; a current measuring unit configured to measure the currentwhich flows on the channel in response to the test voltage; and a resultanalyzing unit configured to analyze a coupling state and a couplingstrength between each of the plurality of coupling units and acorresponding one of the plurality of interface pads based on the testvoltage, and the current which flows on the channel in response to thetest voltage.
 8. The test system of the semiconductor device of claim 7,wherein, as a number of the plurality of coupling units coupled to theplurality of interface pads is increased and a coupling strength betweenthe plurality of coupling units and the plurality of interface pads isincreased, the current which flows on the channel in response to thetest voltage is increased.
 9. The test system of the semiconductordevice of claim 6, wherein each of the plurality of interface pads iscoupled to a current path.
 10. The test system of the semiconductordevice of claim 6, wherein the semiconductor device further comprises aninternal circuit configured to perform an intrinsic operation using asignal that is input or output through the plurality of interface pads;and an electrostatic discharge circuit configured to protect theinternal circuit from an electrostatic that is input through theplurality of interface pads.
 11. The test system of the semiconductordevice of claim 10, wherein the electrostatic discharge circuitcomprises at least one first diode configured to be coupled between apower voltage supply terminal for supplying a power voltage to theinternal circuit and an interface pad corresponding to the at least onefirst diode out of the plurality of interface pads; and at least onesecond diode configured to be coupled between a ground voltage terminalfor supplying a ground voltage to the internal circuit and an interfacepad corresponding to the at least one second diode out of the pluralityof interface pads.
 12. The test system of the semiconductor device ofclaim 11, wherein the test voltage is same as or higher than a sum ofthe power voltage and a threshold voltage of the at least one firstdiode.
 13. A test method for testing a semiconductor device having aplurality of interface pads, comprising: coupling a plurality ofcoupling units to a plurality of interface pads; applying a test voltageto a channel coupled to the plurality of coupling units; and measuring acurrent that flows on the channel in response to the test voltage. 14.The test method for testing the semiconductor device of claim 13,further comprising: analyzing a coupling state and a coupling strengthbetween each of the plurality of coupling units and a corresponding oneof the plurality of interface pads based on the test voltage, and thecurrent which flows on the channel in response to the test voltage. 15.The test method for testing the semiconductor device of claim 13,wherein, as a number of the plurality of coupling units coupled to theplurality of interface pads is increased and a coupling strength betweenthe plurality of coupling units and the plurality of interface pads isincreased, the current which flows on the channel in response to thetest voltage is increased.
 16. The test method for testing thesemiconductor device of claim 13, wherein each of the plurality ofinterface pads is coupled to a current path.